Group III nitride compound semiconductors are direct-transition type semiconductors exhibiting a wide range of emission spectra from UV to red light when used in a device such as a light-emitting device, and have been used in light-emitting devices such as light-emitting diodes (LEDs) and laser diodes (LDs). In addition, due to their broad band gaps, devices employing the aforementioned semiconductors are expected to exhibit reliable operational characteristics at high temperature as compared with those employing semiconductors of other types, and thus application thereof to transistors such as FETs has been energetically studied. Moreover, since Group III nitride compound semiconductors contain no arsenic (As) as a predominant element, application of Group III nitride compound semiconductors to various semiconductor devices has been longed for from the environmental aspect. Generally, these Group III nitride compound semiconductors are formed on a sapphire substrate and also a silicon (Si) substrate.
When a group III nitride compound semiconductor is formed on a silicon (Si) substrate, epitaxial growth process may be carried out under condition that stress owing to misfit of lattice constants between the silicon (Si) substrate and the group III nitride compound semiconductor is always applied. Difference of thermal expansion coefficients between the silicon (Si) substrate and the group III nitride compound semiconductor increases the stress in a cooling process, to thereby generate a lot of cracks (fractures) in the group III nitride compound semiconductor layer. As a result, cracks (fractures) generated in a region where a light-emitting device or other device is formed make the device a defective product and because of that yield rate of the device becomes remarkably poor.
For example, there is a conventional art to zone each growth region as a device forming region (1 mm2 or less) and to form a mask in a pane form at the region besides the growth region. This conventional art enables to suppress generation of cracks (fractures) smaller and confine cracks therein because the individual region can be smaller even when cracks are generated in the device region and stress is not propagated from the adjacent regions form the individual region.
By zoning each device forming region, however, crystal ordinarily grows faster at the edge portion of the region, and that results in forming the region whose central portion is concaved in epitaxial growth. FIG. 11 illustrates such a region. As shown in FIG. 11, a substrate 91, a mask material 92 and a group III nitride compound semiconductor layer 93 are disclosed. Here the group III nitride compound semiconductor layer 93 may not always have a single layer structure. The group III nitride compound semiconductor layer 93 becomes as illustrated in FIG. 11 because the supply amount of group III and group V material is different at the edge portion E and at the central portion M of the device formation region D: the supply amount of group III and group V material is larger at the edge portion E.
Also, when such a selected growth process is carried out so as not to generate cracks, actually stress cannot be relaxed sufficiently and especially threading dislocations do not decrease. In short, generation of cracks (fractures) means relaxation of stress owing to the cracks (fractures). So when the cracks are suppressed, stress is always applied to threading dislocations and deleting each threading dislocation (preventing propagation of each threading dislocation to upward) during epitaxial growth is rather prevented.
The present invention has been accomplished in an attempt to solve the aforementioned problems, and an object of the present invention is to form a separated growth region whose edge portion does not rise in epitaxial growth process.
Other object of the present invention is to suppress cracks (fractures) and decrease threading dislocations in the epitaxial growth of a group III nitride compound semiconductor.
In order to solve the aforementioned problems, the invention drawn to a first feature provides a method for fabricating a Group III nitride compound semiconductor on a substrate through epitaxial growth, which method comprises steps of: forming a mask material, on which a group III nitride compound semiconductor does not epitaxially grow, in grid pattern on the surface of the substrate, zoning the surface of the substrate into each device formation region to be exposed, and forming a consumption region for a group III nitride compound semiconductor at each central portion of a band of the mask formed in grid pattern; and forming a group III nitride compound semiconductor on each of the exposed and zoned substrate surface as the device formation region. Here the central portion of the mask does not necessarily refer to only the central portion continued over the whole area of the band of the mask in grid form but refers to, for example, the area in broken line pattern, scattered dot pattern and other arbitrary pattern. Forming the consumption region may be carried out at the same time of forming the mask material in grid pattern or after forming the mask material in grid pattern.
The invention drawn to a second feature is that the consumption region is formed by exposing some portion of the surface of the substrate which is not used to form a device.
The invention drawn to a third feature is that the consumption region is formed by removing even a portion of the substrate and exposing the substrate surface having a step. The present invention also encompasses the case having a process of removing a portion of the substrate to obtain a substrate surface with a step at first and then forming the mask material in grid pattern.
The invention drawn to a fourth feature is that the area of the device formation region is from 0.01 mm2 to 1 mm2. The invention drawn to a fifth feature is that the area of the device formation region is from 0.01 mm2 to 0.03 mm2.
The invention drawn to a sixth feature is that the substrate is made of silicon (Si). The invention drawn to a seventh feature is that the mask material is mainly made of silicon dioxide (SiO2). The invention drawn to an eighth feature provides a method for fabricating a Group III nitride compound semiconductor further comprising a step of forming a reaction prevention layer mainly made of a monocrystal on each of the exposed zoned substrate surface as the device formation region so that the substrate may not react with the Group III nitride compound semiconductor formed on the substrate during the process of fabricating a Group III nitride compound semiconductor. The present invention does not exclude the case in which the reaction prevention layer is formed in the consumption region. The invention drawn to a ninth feature is that thickness of the reaction prevention layer is from 100 nm to 1 μm. The invention drawn to a tenth feature is that the reaction prevention layer is made of group III nitride compound semiconductor and aluminum (Al) composition of group III material has molar fraction of 30% or more.
The invention drawn to an eleventh feature provides a Group III nitride compound semiconductor device which is formed on the Group III nitride compound semiconductor fabricated by a method for fabricating a Group III nitride compound semiconductor according to any one of the first to tenth feature. The invention drawn to a twelfth feature provides a Group III nitride compound semiconductor light-emitting device which comprises another Group III nitride compound semiconductor layer deposited on the Group III nitride compound semiconductor fabricated by a method for fabricating a Group III nitride compound semiconductor according to any one of the first to tenth feature.
In the epitaxial growth process with each growth region separated by a mask formed in grid pattern, because the consumption region of the Group III nitride compound semiconductor is formed in the central portion of each band of the mask between each adjacent edge portion of the growth region, Group III or Group V raw material is never unnecessarily supplied to the edge portion of the growth region. As a result, difference of group III or group V rare material supply amount to the edge portion and central portion of the device formation region is suppressed and the edge portion of the device region may not be convexity, resulting in remarkably decreasing cracks and defects in the device formation region (the first feature).
The consumption region may be formed by just exposing the substrate surface which is not used to form a device. Alternatively the consumption region may be formed even by removing a portion of the substrate to form a step (the second and third features).
The area of the device formation area may preferably be 0.01 mm2 to 1 mm2 and further preferably 0.01 mm2 to 0.3 mm2. An epitaxial growth layer formed to have several μm of thickness at an area larger than 1 mm2 may have remarkable numbers of cracks owing to stress. When an area is formed to be smaller than 0.3 mm2, each epitaxial growth region is assigned to about a device unit. As a result, yield rate of the device can be further improved (the fourth and fifth features). When an area is formed to be smaller than 0.01 mm2, each epitaxial growth region is not sufficient for an area which one device unit is formed.
The present invention is especially useful when a substrate is made of silicon (Si) whose thermal expansion coefficient is largely different from that of a group III nitride compound semiconductor (the sixth feature). It is simple and easy to use silicon dioxide (SiO2) to form the mask material (the seventh feature). The reaction prevention layer can prevent the substrate from reacting with a group III nitride compound semiconductor deposited thereon during the fabricating process (the eighth feature). Thickness of the reaction prevention layer needs to be at least 100 nm (the ninth feature), and is preferably made of group III nitride compound semiconductor whose aluminum (Al) composition of group III material has molar fraction of 30% or more (the tenth feature). As a result, for example, when AlGaN is formed between the silicon (Si) substrate and gallium nitride (GaN), the silicon (Si) substrate and the gallium nitride (GaN) are formed not to contact with each other directly. That enables to prevent generation of silicon nitride, metal gallium and so on owing to nitride atoms moving in the silicon (Si) substrate from the gallium nitride (GaN). Generally, forming a reaction prevention layer on a substrate which may react with a group III nitride compound semiconductor under a certain condition may be useful and effective.
A device formed on an objective group III nitride compound semiconductor layer formed as described above and a light-emitting device comprising group III nitride compound semiconductor layers which are different from the objective layer can suppress generation of both cracks and threading dislocations at the same time. As a result, a device or a light-emitting device whose yield rate and quality is remarkably high can be obtained (the eleventh and twelfth features).
The invention drawn to a thirteenth feature provides a method for fabricating a Group III nitride compound semiconductor, in which a Group III nitride compound semiconductor is formed on a substrate through epitaxial growth, comprising steps of: a process of forming a mask material, on which a group III nitride compound semiconductor does not epitaxially grow, in grid pattern on the substrate surface, zoning the substrate surface into each region to be exposed; a process of forming a strain relaxation layer comprising group III nitride compound semiconductors, each of which is formed at each two different range of temperature and has equivalent or different composition, deposited alternately on an upper portion of the surface of the substrate which is zoned with each other and is exposed; and a process of forming a group III nitride compound semiconductor on the strain relaxation layer, wherein the group III nitride compound semiconductor deposited in the portion of the substrate surface are separated with each other. Here grid pattern in which the mask material is formed does not necessarily have a square window. Alternatively, it may have, for example, a polygon window like honeycomb. And when group III nitride compound semiconductors are deposited alternately to form the strain relaxation layer, each layer is formed at each different range of temperature, or at the two ranges of temperature which are not needed to be perfectly the same range with each other.
The invention drawn to a fourteenth feature is that the two different ranges of temperature are the range from 200° C. to 600° C. and from 900° C. to 1200° C., respectively. The invention drawn to a fifteenth feature is that the group III nitride compound semiconductor layer formed at the temperature from 200° C. to 600° C. has a thickness from 10 nm to 100 nm and the group III nitride compound semiconductor layer formed at the temperature from 900° C. to 1200° C. has a thickness from 200 nm to 1 μm. The invention drawn to a sixteenth feature is that the process of forming the strain relaxation layer comprises a step of forming a pair of group III nitride compound semiconductor layers at two different ranges of temperature two times or more.
The invention drawn to a seventeenth feature is that an area of the substrate surface which is zoned with each other and is exposed is from 1 mm2 or less. The invention drawn to an eighteenth feature is that an area of the substrate surface which is separated with each other and is exposed is 0.3 mm2 or less.
The invention drawn to a nineteenth feature is that the substrate is made of silicon (Si). The invention drawn to a twentieth feature is that the mask material is mainly made of silicon dioxide (SiO2). The invention drawn to a twenty-first feature provides a method for fabricating a Group III nitride compound semiconductor, further comprising a step of forming a reaction prevention layer mainly made of a monocrystal on the substrate surface which is zoned with each other and is exposed in order to prevent the substrate from reacting with the group III nitride compound semiconductor deposited thereon during production. The reaction prevention layer mainly made of monocrystalline means that the layer is formed under conditions including the temperature at which the reaction prevention layer becomes monocrystalline except for crystal condition around the substrate surface. The invention drawn to a twenty-second feature is that the reaction prevention layer has thickness from 100 nm to 1 μm.
The invention drawn to a twenty-third feature is that the reaction prevention layer is made of a group III nitride compound semiconductor whose aluminum (Al) composition of group III material has molar fraction of 30% or more.
The invention drawn to a twenty-fourth feature provides a group III nitride compound semiconductor device which is fabricated by a method for fabricating a group III nitride compound semiconductor according to any one of the thirteenth to twenty-third features. The invention drawn to a twenty-fifth feature provides a group III nitride compound semiconductor light-emitting device comprising another Group III nitride compound semiconductor layer deposited on the Group III nitride compound semiconductor fabricated by a method for fabricating a Group III nitride compound semiconductor according to any one of the thirteenth to twenty-third features.
Because the mask material on which a group III nitride compound semiconductor can not epitaxially grow is formed in grid pattern on the substrate surface to separate it into each region and exposes them, the area on which the group III nitride compound semiconductor is formed through epitaxial growth can be a small area independent from each other. Then group III nitride compound semiconductors each of which is formed at each different range of temperature and has equivalent or different composition are deposited alternately to form the strain relaxation layer. That can relax stress generated between the substrate and the upper layer formed on the strain relaxation layer, to thereby suppress generation of threading dislocations or extinguish threading dislocations at the upper layer of the layers formed through epitaxial growth. The objective group III nitride compound semiconductor is formed on the strain relaxation layer, and it can prevent generation of cracks and suppress threading dislocations (the thirteenth feature).
The two different ranges of temperature are preferably 200° C. to 600° C. and 900° C. to 1200° C., respectively, and the layer formed at the lower temperature range and the layer formed at the higher temperature range are preferably deposited alternately. Stress is relaxed in a low-temperature growth layer and is more relaxed in the upper part of a high-temperature growth layer because of monocrystalline. As a result, the strain relaxation layer with suppressed threading dislocations can be obtained (the fourteenth feature). The low-temperature growth layer may be preferably formed thinner and the high-temperature growth layer thicker, and each the low-temperature growth layer and the high-temperature growth layer may preferably have thickness of 10 nm to 100 nm and 200 nm to 1 μm, respectively (the fifteenth feature). The more the pair of group III nitride compound semiconductor layers formed at two different ranges of temperature are deposited in the strain relaxation layer, the more stress may be relaxed. So a pair of a low-temperature growth layer and a high-temperature growth layer may be preferably formed in the strain relaxation layer two times or more (the sixteenth feature).
An area of the substrate surface which is zoned with each other and is exposed may preferably be 0.01 mm2 to 1 mm2 and further preferably 0.01 mm2 to 0.3 mm2. An epitaxial growth layer formed to have several μm of thickness at an area larger than 1 mm2 may have remarkable numbers of cracks owing to stress. When the exposed area is formed to be smaller than 0.3 mm2, each epitaxial growth region is about a device unit. As a result, yield rate of the device can be further improved (the seventeenth and eighteenth features). When the exposed area is formed to be smaller than 0.01 mm2, each epitaxial growth region is not sufficient for an area on which one device unit is formed.
The present invention is especially useful when a substrate is made of silicon (Si) whose thermal expansion coefficient is largely different from that of a group III nitride compound semiconductor (the ninteenth feature). It is simple and easy to use silicon dioxide (SiO2) to form the mask material (the twentieth feature). The reaction prevention layer which is mainly made of monocrystalline and is formed on the exposed substrate surface can prevent the substrate from reacting with the group III nitride compound semiconductor deposited thereon owing to stress generated during the fabricating process such as epitaxial growth, forming electrode, photolithography, etching and other treatment, heating or cooling process down to the ambient temperature (the twenty-first feature). Thickness of the reaction prevention layer needs to be at least 100 nm (the twenty-second feature), and is preferably made of group III nitride compound semiconductor whose aluminum (Al) composition of group III material has molar fraction of 30% or more (the twenty-third feature). As a result, for example, when AlGaN is formed between the silicon (Si) substrate and gallium nitride (GaN), the silicon (Si) substrate and the gallium nitride (GaN) are formed not to contact with each other directly. That enables to prevent generation of silicon nitride, metal gallium and so on owing to nitride atoms moving in the silicon (Si) substrate from the gallium nitride (GaN). Generally, forming a reaction prevention layer on a substrate which may react with a group III nitride compound semiconductor under a certain condition may be useful and effective.
A device formed on an objective group III nitride compound semiconductor layer formed as described above and a light-emitting device comprising group III nitride compound semiconductor layers which are different from the objective layer can suppress generation of both cracks and threading dislocations at the same time. As a result, a device or a light-emitting device whose yield rate and quality is remarkably high can be obtained (the twenty-fourth and twenty-fifth features). Forming layers on each zoned growth region helps to decrease warp of the substrate remarkably compared with when layers are deposited on the entire surface of the substrate. As a result, yield rate of the device may be improved.